The present invention relates to digital multi-axis robot controls and more particularly to interface systems for microprocessors coordinated to operate as a servo controller within the robot control looping.
In a multi-axis robot control, a significant amount of mathematical processing capability is required in a single control microprocessor for the implementation of servo control calculations at any one control loop level in the respective control channels for the robot axes. The total processing capability needed for all control levels in all of the axis control channels is extensive.
Generally, commercially available microprocessors have inadequate processing capability to meet the needs of multi-axis robot control. Therefore, multiple interactive microprocessors need to be harnessed to meet the needs of multi-axis robot control. A completely digital robot control employing interactive microprocessors and providing improvement in robot performance and robot control with cost effectiveness and manufacturing economy is disclosed in the referenced copending applications.
As disclosed in U.S. Pat. No. 4,763,055, a microprocessor servo control is configured with a first microprocessor having high data processing capability and a digital signal processor having high computational capability. In coordinated operation controlled by the first microprocessor, the two processors provide more than adequate servo control processing capability in a multi-axis robot control system.
In the referenced and other multi-microprocessor control configurations, provision has to be made, and preferably efficiently made, for implementing inter-microprocessor communication. Thus, in a paired microprocessor arrangement, command information and data must be transferred from the controlling microprocessor to the slave microprocessor, status information and data must be transferred from the slave microprocessor to the controlling microprocessor and provision must be made for interfacing upward and downward control communications with the inter-microprocessor interface.
In the case of digital signal processors and other cases where operations in one of the microprocessors cannot be suspended, inter-processor communication schemes have typically required direct intervention by both microprocessors in the communication task. Such administrative overhead can consume a significant portion of available processing capability and thereby tend to defeat the purpose in using multi-processors in the first place.